--
-- psk_mod.vhd
--
-- This module demonstrates the use of the NCO module to implement a
-- simple Phase Shift Keying modulator.
--
-- Ports:
--
--   psk_clk    - The clock (at sampling frequency).
--   datain     - Data to be modulated.
--   psk_output - PSK modulated output.
--
-- Dependencies:
--
--   * nco.vhd
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY psk_mod IS
  PORT(psk_clk: IN std_logic;
       datain: IN std_logic_vector(0 downto 0);
       psk_output: OUT std_logic_vector(7 downto 0));
END psk_mod;

ARCHITECTURE archpsk OF psk_mod IS
  signal f: std_logic_vector(23 downto 0);
  signal period: std_logic;
BEGIN

  -- change this to use a different carrier frequency.
  f <="000000100000000000000000";

  osc: work.nco
    GENERIC MAP(24,9,8,1)
    PORT MAP(psk_clk, f, datain, psk_output, period);

END archpsk;

--
-- END psk_mod.vhd
--